Classification and Generation of Schedules for VLIW Processors
Christoph Kessler and Andrzej Bednarski
We identify and analyze different classes of schedules for VLIW processors.
The classes are induced by various common techniques for generating
or enumerating them, such as integer linear programming or
list scheduling with backtracking.
In particular, we study the relationship between VLIW schedules
and their equivalent linearized forms (which may be used, e.g.,
with superscalar processors), and we identify classes of VLIW schedules
that can be created from a linearized form using an in-order
VLIW compaction heuristic, which is just the static equivalent
of the dynamic instruction dispatch algorithm of in-order issue
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