CPC 2006 CPC 2006

Call for Participation
Current List of
Program (List of Talks)
Registration Form
Travel Information

Funded by the Vicerreitoría de Investigación of the University of A Coruña and the Ministry of Education and Science of Spain

Universidade de A Coruña Ministerio de
		      Educaciˇn y Ciencia

Extracting Threads Using Traces for System on a Chip

Eric Petit and Franšois Bodin
Irisa, Campus de Beaulieu, Rennes, France

Most current embedded systems are System on a Chip that integrate multiple CPU with heterogeneous memory systems and computation capabilities. The design of these SoC starts from partitioning/parallelizing the applications that are then mapped on the SoC computing units. In many cases, the input of the partition process is a sequential program written in C. Due to pointer aliasing issues, these programs are difficult to analyze statically. Furthermore, in some cases it is necessary to go beyond loop parallelism. As a consequence, automatic static parallelization techniques cannot be used. In practice, the partitioning process is often performed by "hand". This strongly limits the exploration of the SoC design space.

In this work, we address the issue of detecting speculative threads in C programs. They can be used as a basis for partitioning embedded applications for SoC. We focus on the exploration phase. It includes detection, selection and characterization of potential threads. To build the threads we use a speculative model that, contrary to previous approach, does not require a shared memory. The speculation is performed on control flow, data dependencies and data structure layout. The threads are built using profiling and hot-paths information.╩╩

Preliminary results show that the approach is able to capture and to characterize the main computation kernels of embedded applications.

Back to the Workshop Program 

Please contact our webadmin with any comments or changes.