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Funded by the Vicerreitoría de Investigación of the University of A Coruña and the Ministry of Education and Science of Spain 
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Parallelizing Compilation Scheme for Reduction of Power Consumption of Chip Multiprocessors
Jun Shirako1, Naoto Oshiyama1, Yasutaka Wada1, Hiroaki Shikano2, Keiji Kimura1,2 and Hironori Kasahara1,2
1 Department of Computer Science, Waseda
University, Tokyo, Japan
2 Advanced Chip Multiprocessor Research
Institute, Waseda University, Tokyo,
Japan
With the advance of semiconductor integration technology,
chip multiprocessor architectures, or
multi core processor architectures have attracted
much attention to achieve high effective performance,
low price and short development period.
To this end, a parallelizing compiler for chip multiprocesors
is expected that allows us to parallelize program effectively,
to control the voltage and clock frequency of
computing resources and storages carefully inside an
application program.
This paper proposes a power reduction parallelizing
compilation scheme under the multigrain parallel processing
environment that controls Voltage/Frequency and power
supply of each processor core on a chip.
Also, the performance of the proposed power saving parallelizing
compilation scheme on a chip multiprocessor
using several benchmark programs is evaluated.
