CPC 2006 CPC 2006

Call for Participation
Current List of
Program (List of Talks)
Registration Form
Travel Information

Funded by the Vicerreitoría de Investigación of the University of A Coruña and the Ministry of Education and Science of Spain

Universidade de A Coruña Ministerio de
		      Educación y Ciencia

Semi-Static Performance Prediction for MPSoC Platforms

Ana Lucía Varbanescu, Henk Sips and Arjan van Gemund
Department of Computer Science, Delft University of Technology, The Netherlands

MPSoC platforms are a hot topic in the industry's high-performance computing trend, advertising new uses for parallel programming techniques and technologies in real-time applications. While the processing power of these platforms is increasing, their memory constraints - both in size and structure - are making things more difficult. Adapting traditional parallel programming for these platforms is cumbersome, usually implying that balanced usage of their complex hardware resources is almost impossible. Moreover, their performance is far from predictable, which is definitely toxic in the real-time applications environment. In fact, performance evaluation for these types of platforms still relies solely on trace-based or even full-flavour simulation. This paper presents a different approach in trying to program and use MPSoC platforms: by means of disciplined programming - namely, using the Series-Parallel (SP) programming model - we claim that performance analysis and prediction are achievable within reasonable limits. This claim is based on experiments with an MPSoC platform, imposing SPC-programming by using the Spar/Java parallel programming language. The performance analysis is done by coupling the PAMELA performance analysis tool to the Spar/Java compiler. Pamela performance analysis methodology is based on combining a generated SPC model of a parallel program with a MPSoC machine model comprising the essentials of the hardware architecture. The Spar-Pamela combination has already been proven successful in previous performance analysis experiments on general purpose parallel platforms. For MPSoC platforms several enhancements have been made in order to be able to model the fine architectural details, while keeping the entire modeling process as straightforward as possible. We will present the results of running a small set of benchmark applications in Spar/Java on a simulator of an MPSoC platform and compare these results with Pamela predictions of the same code.

Back to the Workshop Program 

Please contact our webadmin with any comments or changes.