(Instructions for authors can be found here)

Workshop Program

	Day 1	Day 2	Day 3
	Monday, Jan 9	Tuesday, Jan 10	Wednesday, Jan 11
08:15-08:45	Registration
08:45-09:00	Welcome Address
09:00-10:30	Session 1	Session 4	Session 8
10:30-11:00	Coffee Break	Coffee Break	Coffee Break
11:00-12:30	Session 2	Session 5	Session 9
12:30-14:00	Lunch	Lunch	Lunch
14:00-15:30	Session 3	Session 6	Session 10
15:30-16:00		Coffee Break	Coffee Break
16:00-17:30		Session 7	Session 11
	Social Event	Workshop Dinner	End of Workshop

Session 1: Embedded Systems
Session chair: Michael O'Boyle

• Semi-Static Performance Prediction for MPSoC Platforms
  Ana Lucía Varbanescu, Henk Sips and Arjan van Gemund
  Department of Computer Science, Delft University of Technology, The Netherlands
  
• Automatic Customization of Embedded Applications for Enhanced Performance and Reduced Power using Optimizing Compiler Techniques
  Emre Özer¹, Andy Nisbet², Milan Tichy³ and David Gregg^{3
  1} ARM Ltd., Cambridge, UK
  ² Manchester Metropolitan University, UK
  ³ University of Dublin, Ireland
  
• Extracting Threads Using Traces for System on a Chip
  Eric Petit and François Bodin
  Irisa, Campus de Beaulieu, Rennes, France

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Session 2: Compiling for VLIW Processors
Session chair: Peter Knijnenburg

• Register Allocation for VLIW DSP Processors with Irregular Register Files
  Yung-Chia Lin, Yi-Ping You and Jenq Kuen Lee
  National Tsing Hua University, Hsinchu, Taiwan
• Classification and Generation of Schedules for VLIW Processors
  Christoph Kessler and Andrzej Bednarski
  PELAB, Departement of Computer and Information Science, Linköpings Universitet, Sweden
• Integer Linear Programming versus Dynamic Programming for Optimal Integrated VLIW Code Generation
  Andrzej Bednarski and Christoph Kessler
  PELAB, Departement of Computer and Information Science, Linköpings Universitet, Sweden

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Session 3: Exploiting Accelerating Hardware
Session chair: Manuel Arenaz

• Accelerating a C++ Image Processing Library using a GPU (Preliminary Report)
  Jay L. T. Cornwall, Olav Beckmann and Paul H. J. Kelly
  Department of Computing, Imperial College London, UK
• An Empirical Study of Some x86 SIMD Integer Extensions
  Isabelle Hurbain and Georges-André Silber
  Centre de Recherche de Informatique, Mines de Paris, Fontainebleau, France

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Session 4: Memory Hierarchy Optimizations
Session chair: Alain Darte

• Optimizing Cache Locality by Static Array Redimensioning
  E. Herruzo¹, E.L. Zapata² and O. Plata^{2
  1} Department of Electronics, University of Córdoba, Spain
  ² Department of Computer Architecture, University of Málaga, Spain
• ESODYP: An Entirely Software and Dynamic Data Prefetcher based on a Markov Model
  Jean Christophe Beyler and Philippe Clauss
  Université de Strasbourg, LSIIT/ICPS, Illkirch-Graffenstaden, France
• Empirical Evaluation Of Compressive Hashing
  Muthulakshmi Muthukumarasamy and Henry Dietz
  Department of Electrical and Computer Engineering, University of Kentucky, USA

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Session 5: Analysis Algorithms
Session chair: Barbara Chapman

• Shape Analysis for Dynamic Data Structures based on Coexistent Links Sets
  A. Tineo, F. Corbera, A. Navarro, R. Asenjo and E.L. Zapata
  Department of Computer Architecture, University of Málaga, Spain
• The New Framework for Loop Nest Optimization in GCC: from Prototyping to Evaluation
  Sebastian Pop¹, Albert Cohen², Pierre Jouvelot¹ and Georges-André Silber^{1
  1} Centre de Recherche en Informatique, Mines de Paris, Fontainebleau, France
  ² ALCHEMY Group, INRIA Futurs, Orsay, France
• Automated and Accurate Cache Behavior Analysis for Codes with Irregular Access Patterns
  Diego Andrade, Manuel Arenaz, Basilio B. Fraguela, Juan Touriño and Ramón Doallo
  Computer Architecture Group, University of A Coruña, Spain

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Session 6: Domain-Specific Optimization
Session chair: Basilio Fraguela

• Optimizing Sorting with Genetic Algorithms
  Xiaoming Li, María Jesús Garzarán and David Padua
  Department of Computer Science, University of Illinois at Urbana-Champaign, USA
• Parallel Visualization using the Domain-Specific Interpreter Pattern
  Karen Osmond, Olav Beckmann, Anthony J. Field and Paul H. J. Kelly
  Department of Computing, Imperial College London, UK
• Efficient Search-Space Pruning for Integrated Fusion and Tiling Transformations
  Xiaoyang Gao¹, Sriram Krishnamoorthy¹, Swarup Kumar Sahoo¹, Chi-Chung Lam¹, Gerald Baumgartner², J. Ramanujam³ and P. Sadayappan^{1
  1} Department of Computer Science and Engineering, The Ohio State University, USA
  ² Department of Computer Science, Louisiana State University, USA
  ³ Department of Electrical and Computer Engineering, Louisiana State University, USA

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Session 7: Compiling Java
Session chair: Henk Sips

• JaMP: An Implementation of OpenMP for a Java DSM
  M. Klemm, M. Bezold, R. Veldema and M. Phipippsen
  University of Erlangen-Nuremberg, Erlangen, Germany
• Improving the Java Virtual Machine using Type-Separated Bytecode
  Philipp Adler and Wolfram Amme
  Friedrich-Schiller-Universität, Jena, Germany
• Automatic Tuning of Inlining Heuristics for Java JIT Compilation
  John Cavazos and Michael F.P. O'Boyle
  Institute for Computing Systems Architecture (ICSA), School of Informatics, University of Edinburgh, UK

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Session 8: Synchronization and Consistency
Session chair: Christoph Kessler

• Fast Synchronization for Quasi-Immutable Objects
  Hiroyasu Nishiyama¹ and Kei Nakajima^{2
  1} Systems Development Laboratory, HITACHI, Japan
  ² Software Division, HITACHI, Japan
• Compiler Techniques for High Performance Sequentially Consistent Java Programs
  Zehra Sura¹, Xing Fang², Chi-Leung Wong³, Samuel P. Midkiff², Jaejin Lee⁴ and David Padua^{3
  1} IBM T.J. Watson Research Center, USA
  ² Purdue University, USA
  ³ University of Illinois at Urbana-Champaign, USA
  ⁴ Seoul National University, Korea
  
• Optimal Linear-Time Barrier Placement
  Alain Darte¹ and Rob Schreiber^{2
  1} CNRS, LIP, ENS-Lyon, France
  ² Hewlett Packard Laboratories, Palo Alto, USA

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Session 9: Thread-Level Parallelism
Session chair: Juan Touriño

• A Microthreaded Architecture and its Compiler
  T. Bernard, K. Bousias, B. de Geus, M. Lankamp, L. Zhang, A. Pimentel, P.M.W. Knijnenburg and C.R. Jesshope
  Computer Systems Architecture Group, Informatics Institute, University of Amsterdam, The Netherlands
• The Mitosis Compiler: Speculative Parallelization using Pre-Computation
  Carlos García Quiñones¹, Carlos Madriles¹, Pedro Marcuello¹, Antonio González^1,2 and Dean Tullsen^{3
  1} Intel Barcelona Research Center, Barcelona, Spain
  ² Department of Computer Architecture, Universitat Politcénica de Catalunya, Barcelona, Spain
  ³ Department of Computer Science and Engineering, UC San Diego, USA
  
• OpenUH: An Optimizing, Portable OpenMP Compiler
  Chunhua Liao¹, Oscar Hernandez¹, Barbara Chapman¹, Wenguang Chen² and Weimin Zheng^{2
  1} Computer Science Department, University of Houston, USA
  ² Computer Science Department, Tsinghua University, China

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Session 10: Parallel Processing
Session chair: David Padua

• Adaptive Selection of Communication Methods to Optimize Collective MPI Operations
  Olaf Hartmann¹, Matthias Kühnemann¹, Thomas Rauber² and Gudula Rünger^{1
  1} Department of Computer Science, Chemnitz University of Technology, Germany
  ² Department of Mathematics and Physics, Bayreuth University, Germany
• Dynamic Scheduling of Parallel Tasks in Multiprogrammed Parallel Processing Systems
  Arun Kejariwal¹, Alexandru Nicolau¹ and Constantine D. Polychronopoulos^{2
  1} Center for Embedded Computer Systems, University of California at Irvine, USA
  ² Center of Supercomputing Research and Development, University of Illinois at Urbana-Champaign, USA
• Portable Checkpointing of MPI Applications
  Gabriel Rodríguez, María J. Martín, Patricia González, Juan Touriño and Ramón Doallo
  Computer Architecture Group, University of A Coruña, Spain

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Session 11: Optimizations
Session chair: Ramón Doallo

• Supporting Higher-Order Virtualization
  Jeremy Singer, Chris Kirkham and Ian Watson
  School of Computer Science, University of Manchester, UK
• Parallelizing Compilation Scheme for Reduction of Power Consumption of Chip Multiprocessors
  Jun Shirako¹, Naoto Oshiyama¹, Yasutaka Wada¹, Hiroaki Shikano², Keiji Kimura^1,2 and Hironori Kasahara^{1,2
  1} Department of Computer Science, Waseda University, Tokyo, Japan
  ² Advanced Chip Multiprocessor Research Institute, Waseda University, Tokyo, Japan
• Toward Remote Object Coherence with Compiled Object Serialization for Distributed Computing with XML Web Services
  Robert van Engelen¹, Wei Zhang¹ and Madhusudhan Govindaraju^{2
  1} Department of Computer Science, Florida State University, USA
  ² Department of Computer Science, State University of New York (SUNY) at Binghamton, USA

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Social event:

Guided visit to Santiago de Compostela. Bus leaves from the hotel at 15:30. Back to the hotel at approximately 20:00.

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Workshop dinner:

Dinner at the Domus Restaurant at 21:00. Located in the Casa del Hombre "Domus" Museum (within walking distance from the hotel).

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